1. Technical Field
The invention relates generally to microelectronics fabrication, and more particularly, to methods and structure with reduced stacking faults in epitaxially grown silicon.
2. Background Art
Performance improvement of semiconductor devices is a never-ending endeavor for manufacturers of those devices. One challenge currently faced by the semiconductor industry is implementing memory and logic devices on a single chip while maintaining process simplicity and transistor performance. These devices are referred to as “system-on-chips” (SoC) because the electronics for a complete, working product are contained on a single chip. One approach that is currently employed to improve performance of a SoC is to fabricate the different types of logic devices on silicon substrates having optimal surface orientations. As used herein, “surface orientation” refers to the crystallographic structure or periodic arrangement of silicon atoms on the surface of a wafer. In particular, an n-type field effect transistor (nFET) can be optimized by being generated on silicon having a (100) surface orientation, while a p-type field effect transistor (pFET) can be optimized by being generated on silicon having a (110) surface orientation. In addition, memory devices and nFETs are typically optimized when generated on silicon-on-insulator (SOI) substrates, while pFETs are typically optimized when generated on bulk silicon.
Fabricating the above-described hybrid orientation logic devices presents challenges. One widely accepted approach to generate the hybrid surface orientations includes bonding a silicon-on-insulator (SOI) wafer atop a bulk silicon substrate having a different surface orientation than the silicon of the SOI wafer. The bulk silicon surface orientation can be epitaxially grown from an opening to the bulk silicon substrate through the SOI wafer. For instance, if an nFET is to be created on a (100) surface orientation of the SOI wafer, the pFET can be generated on epitaxially grown silicon extending through the SOI wafer having a (110) surface orientation.
One challenge relative to the above-described technique, however, is growing stacking fault reduced structure. Stacking faults are planer defects which often occur in epitaxial films when the crystal stacking sequence is disrupted because of local environmental changes during growth, e.g., impurities or surface imperfections. The defects are characterized by the fact that the displacement between planes on either side of the defect is not a perfect crystal translation vector for the material in question. For instance, for face center cubic (fcc) materials, crystal grows in the <111> direction according to the well known close packing stacking sequence—ABCABC, where A, B and C are distinct stacking sites between which the crystal translation vector is (½) [110]. A stacking sequence of ABCAB//ABC contains a fault between planes “B” and “A” indicated by “//” and is termed an intrinsic stacking fault and can be thought of as the removal of a crystal plane (“C” in this case). In contrast, a stacking sequence of ABCA/C/BCABC is termed an extrinsic stacking fault and can be thought of as the insertion of an extra plane into the stacking sequence (in this case “C”).
FIGS. 1A-B show one example of a technique for generated hybrid surface orientation areas on a single wafer. As shown in FIG. 1A, an opening 10 to a silicon substrate 12 is made through an SOI wafer 14 for epitaxially growing silicon having a surface orientation of substrate 12. A silicon nitride layer 22 is formed over opening 10. SOI wafer 14 includes a silicon layer 16 within a silicon oxide layer 18. As shown in FIG. 1B, when silicon nitride liner 22 is opened to silicon substrate 12, positively sloped corners 24 are created. As also shown in FIG. 1B, as silicon 26 is epitaxially grown, stacking faults 28 are created in silicon 26 in opening 10 (FIG. 1A) by positively sloped corners 24 at the bottom of opening 10 (FIG. 1A). In particular, as atoms stack on top of each other during epitaxial growth, they form in an orderly fashion. However, if a positive sloped corner 24 near a surface of silicon substrate 12 exists, the stacking sequence is disrupted by two causes. First, atomic arrangement on silicon nitride liner 22 is different from the atomic arrangement on the bare surface of silicon substrate 12. Second, since there is a slope in silicon nitride liner 22 (sloped corners 24) compared to the flat surface of silicon substrate 12, the atom stacking on top of each other on silicon nitride liner 24 is not the same as the bare surface of silicon substrate 12. As a result of the foregoing, the crystalline growth at positive sloped corners 24 is disrupted, causing a stacking fault 28 (i.e., missing or adding an extra plane (with <110> orientation based illustrative surface orientations)) from the foot of the side wall.
Subsequently, as shown in FIG. 1C, when a sharp edge 30 is formed at the bottom of silicon 26, grown in opening 10 (FIG. 1A), stacking faults 28 create problems for devices, such as leakage or non functional devices.